How to properly clear pending External Interrupt in LPC17xx?
I am writing an program for the LPC1768 that simulates a state machine. In the beginning states the program must be able to handle button interrupts (EINT1 EINT2). Then interrupts are disabled on the NVIC (Nested Vector Interrupt Controller) but are still sent to it, becoming pending. If I re-enable the interrupts they are handled, so i tried to clear the pending ones before doing that. It solves the problem but then new interrupts aren't seen anymore by the NVIC and I don't understand why.
I disable interrupt using:
NVIC_DisableIRQ(EINT2_IRQn);
NVIC_DisableIRQ(EINT1_IRQn);
when it's time I clear pending ones and re-enable:
NVIC_ClearPendingIRQ(EINT1_IRQn);
NVIC_ClearPendingIRQ(EINT2_IRQn);
NVIC_EnableIRQ(EINT2_IRQn);
NVIC_EnableIRQ(EINT1_IRQn);
The code was not executed on the board but only debugged using the keil uvision5 software.
embedded interrupt lpc
asked Dec 31 '18 at 9:48
Pietro ChiavassaPietro Chiavassa
12
|
show 2 more comments
I am writing an program for the LPC1768 that simulates a state machine. In the beginning states the program must be able to handle button interrupts (EINT1 EINT2). Then interrupts are disabled on the NVIC (Nested Vector Interrupt Controller) but are still sent to it, becoming pending. If I re-enable the interrupts they are handled, so i tried to clear the pending ones before doing that. It solves the problem but then new interrupts aren't seen anymore by the NVIC and I don't understand why.
I disable interrupt using:
NVIC_DisableIRQ(EINT2_IRQn);
NVIC_DisableIRQ(EINT1_IRQn);
when it's time I clear pending ones and re-enable:
NVIC_ClearPendingIRQ(EINT1_IRQn);
NVIC_ClearPendingIRQ(EINT2_IRQn);
NVIC_EnableIRQ(EINT2_IRQn);
NVIC_EnableIRQ(EINT1_IRQn);
The code was not executed on the board but only debugged using the keil uvision5 software.
embedded interrupt lpc
asked Dec 31 '18 at 9:48
Pietro ChiavassaPietro Chiavassa
12
Code you are showing is general for ARM-Cortex-M CPUs. If you clear pending bit in NVIC, there is still possibility that your peripheral sets it again, so make sure that you also clear all peripheral bits.
– tilz0R
Dec 31 '18 at 9:50
@tilz0R Hi, the problem is not that the pending bit i re-set, in fact it isn't. the problem is that interrupts from the peripheral are not seen anymore by the nvic
– Pietro Chiavassa
Dec 31 '18 at 9:55
Did you disable global interrupts using__disable_irq()function? If so, enable back with__enable_irq().
– tilz0R
Dec 31 '18 at 9:57
i didn't do that because i also use a timer and i need to handle its interrupts. And those work even if the buttons don't
– Pietro Chiavassa
Dec 31 '18 at 9:59
Then focus on EINT peripheral and GPIO configuration. Code you posted looks ok.
– tilz0R
Dec 31 '18 at 10:00
|
show 2 more comments
I am writing an program for the LPC1768 that simulates a state machine. In the beginning states the program must be able to handle button interrupts (EINT1 EINT2). Then interrupts are disabled on the NVIC (Nested Vector Interrupt Controller) but are still sent to it, becoming pending. If I re-enable the interrupts they are handled, so i tried to clear the pending ones before doing that. It solves the problem but then new interrupts aren't seen anymore by the NVIC and I don't understand why.
I disable interrupt using:
NVIC_DisableIRQ(EINT2_IRQn);
NVIC_DisableIRQ(EINT1_IRQn);
when it's time I clear pending ones and re-enable:
NVIC_ClearPendingIRQ(EINT1_IRQn);
NVIC_ClearPendingIRQ(EINT2_IRQn);
NVIC_EnableIRQ(EINT2_IRQn);
NVIC_EnableIRQ(EINT1_IRQn);
The code was not executed on the board but only debugged using the keil uvision5 software.
embedded interrupt lpc
asked Dec 31 '18 at 9:48
Pietro ChiavassaPietro Chiavassa
12
I am writing an program for the LPC1768 that simulates a state machine. In the beginning states the program must be able to handle button interrupts (EINT1 EINT2). Then interrupts are disabled on the NVIC (Nested Vector Interrupt Controller) but are still sent to it, becoming pending. If I re-enable the interrupts they are handled, so i tried to clear the pending ones before doing that. It solves the problem but then new interrupts aren't seen anymore by the NVIC and I don't understand why.
I disable interrupt using:
NVIC_DisableIRQ(EINT2_IRQn);
NVIC_DisableIRQ(EINT1_IRQn);
when it's time I clear pending ones and re-enable:
NVIC_ClearPendingIRQ(EINT1_IRQn);
NVIC_ClearPendingIRQ(EINT2_IRQn);
NVIC_EnableIRQ(EINT2_IRQn);
NVIC_EnableIRQ(EINT1_IRQn);
The code was not executed on the board but only debugged using the keil uvision5 software.
embedded interrupt lpc
embedded interrupt lpc
asked Dec 31 '18 at 9:48
Pietro ChiavassaPietro Chiavassa
12
asked Dec 31 '18 at 9:48
Pietro ChiavassaPietro Chiavassa
12
edited Dec 31 '18 at 10:47
Pietro Chiavassa
asked Dec 31 '18 at 9:48
Pietro ChiavassaPietro Chiavassa
12
asked Dec 31 '18 at 9:48
Pietro ChiavassaPietro Chiavassa
12
asked Dec 31 '18 at 9:48
Pietro ChiavassaPietro Chiavassa
12
12
Code you are showing is general for ARM-Cortex-M CPUs. If you clear pending bit in NVIC, there is still possibility that your peripheral sets it again, so make sure that you also clear all peripheral bits.
– tilz0R
Dec 31 '18 at 9:50
@tilz0R Hi, the problem is not that the pending bit i re-set, in fact it isn't. the problem is that interrupts from the peripheral are not seen anymore by the nvic
– Pietro Chiavassa
Dec 31 '18 at 9:55
Did you disable global interrupts using__disable_irq()function? If so, enable back with__enable_irq().
– tilz0R
Dec 31 '18 at 9:57
i didn't do that because i also use a timer and i need to handle its interrupts. And those work even if the buttons don't
– Pietro Chiavassa
Dec 31 '18 at 9:59
Then focus on EINT peripheral and GPIO configuration. Code you posted looks ok.
– tilz0R
Dec 31 '18 at 10:00
|
show 2 more comments
Code you are showing is general for ARM-Cortex-M CPUs. If you clear pending bit in NVIC, there is still possibility that your peripheral sets it again, so make sure that you also clear all peripheral bits.
– tilz0R
Dec 31 '18 at 9:50
@tilz0R Hi, the problem is not that the pending bit i re-set, in fact it isn't. the problem is that interrupts from the peripheral are not seen anymore by the nvic
– Pietro Chiavassa
Dec 31 '18 at 9:55
Did you disable global interrupts using__disable_irq()function? If so, enable back with__enable_irq().
– tilz0R
Dec 31 '18 at 9:57
i didn't do that because i also use a timer and i need to handle its interrupts. And those work even if the buttons don't
– Pietro Chiavassa
Dec 31 '18 at 9:59
Then focus on EINT peripheral and GPIO configuration. Code you posted looks ok.
– tilz0R
Dec 31 '18 at 10:00
Code you are showing is general for ARM-Cortex-M CPUs. If you clear pending bit in NVIC, there is still possibility that your peripheral sets it again, so make sure that you also clear all peripheral bits.
– tilz0R
Dec 31 '18 at 9:50
Code you are showing is general for ARM-Cortex-M CPUs. If you clear pending bit in NVIC, there is still possibility that your peripheral sets it again, so make sure that you also clear all peripheral bits.
– tilz0R
Dec 31 '18 at 9:50
@tilz0R Hi, the problem is not that the pending bit i re-set, in fact it isn't. the problem is that interrupts from the peripheral are not seen anymore by the nvic
– Pietro Chiavassa
Dec 31 '18 at 9:55
@tilz0R Hi, the problem is not that the pending bit i re-set, in fact it isn't. the problem is that interrupts from the peripheral are not seen anymore by the nvic
– Pietro Chiavassa
Dec 31 '18 at 9:55
Did you disable global interrupts using
__disable_irq() function? If so, enable back with __enable_irq().– tilz0R
Dec 31 '18 at 9:57
Did you disable global interrupts using
__disable_irq() function? If so, enable back with __enable_irq().– tilz0R
Dec 31 '18 at 9:57
i didn't do that because i also use a timer and i need to handle its interrupts. And those work even if the buttons don't
– Pietro Chiavassa
Dec 31 '18 at 9:59
i didn't do that because i also use a timer and i need to handle its interrupts. And those work even if the buttons don't
– Pietro Chiavassa
Dec 31 '18 at 9:59
Then focus on EINT peripheral and GPIO configuration. Code you posted looks ok.
– tilz0R
Dec 31 '18 at 10:00
Then focus on EINT peripheral and GPIO configuration. Code you posted looks ok.
– tilz0R
Dec 31 '18 at 10:00
|
show 2 more comments
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Code you are showing is general for ARM-Cortex-M CPUs. If you clear pending bit in NVIC, there is still possibility that your peripheral sets it again, so make sure that you also clear all peripheral bits.
– tilz0R
Dec 31 '18 at 9:50
@tilz0R Hi, the problem is not that the pending bit i re-set, in fact it isn't. the problem is that interrupts from the peripheral are not seen anymore by the nvic
– Pietro Chiavassa
Dec 31 '18 at 9:55
Did you disable global interrupts using
__disable_irq()function? If so, enable back with__enable_irq().– tilz0R
Dec 31 '18 at 9:57
i didn't do that because i also use a timer and i need to handle its interrupts. And those work even if the buttons don't
– Pietro Chiavassa
Dec 31 '18 at 9:59
Then focus on EINT peripheral and GPIO configuration. Code you posted looks ok.
– tilz0R
Dec 31 '18 at 10:00