How can I use Synopsys VCS for dynamic voltage scaling in a micro processor?
I'm trying to simulate a RISCV based processor on Synopsys VCS with RTL design (verilog). I would like to change the voltage dynamically while the simulation is running. Is there any tool in Synopsys that can be used for performing dynamic voltage scaling in a microprocessor. Or is it possible to do so in testbench?
riscv synopsys-vcs
asked Dec 28 '18 at 21:15
deadpool3deadpool3
1
add a comment |
I'm trying to simulate a RISCV based processor on Synopsys VCS with RTL design (verilog). I would like to change the voltage dynamically while the simulation is running. Is there any tool in Synopsys that can be used for performing dynamic voltage scaling in a microprocessor. Or is it possible to do so in testbench?
riscv synopsys-vcs
asked Dec 28 '18 at 21:15
deadpool3deadpool3
1
add a comment |
I'm trying to simulate a RISCV based processor on Synopsys VCS with RTL design (verilog). I would like to change the voltage dynamically while the simulation is running. Is there any tool in Synopsys that can be used for performing dynamic voltage scaling in a microprocessor. Or is it possible to do so in testbench?
riscv synopsys-vcs
asked Dec 28 '18 at 21:15
deadpool3deadpool3
1
I'm trying to simulate a RISCV based processor on Synopsys VCS with RTL design (verilog). I would like to change the voltage dynamically while the simulation is running. Is there any tool in Synopsys that can be used for performing dynamic voltage scaling in a microprocessor. Or is it possible to do so in testbench?
riscv synopsys-vcs
riscv synopsys-vcs
asked Dec 28 '18 at 21:15
deadpool3deadpool3
1
asked Dec 28 '18 at 21:15
deadpool3deadpool3
1
asked Dec 28 '18 at 21:15
deadpool3deadpool3
1
asked Dec 28 '18 at 21:15
deadpool3deadpool3
1
asked Dec 28 '18 at 21:15
deadpool3deadpool3
1
1
add a comment |
add a comment |
1 Answer
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There is no concept of analog values such as voltage in verilog or VHDL. Just digital signals and simple timing.
Analog simulations are done in other languages like SPICE.
answered Dec 28 '18 at 23:24
serpixoserpixo
1236
Thank you for your answer. Can we change analog values after synthesis and getting gate level netlist?
– deadpool3
Jan 2 at 21:36
This is out of my expertise, so I'm not sure. It may be possible to export from a gate level netlist to spice netlist, but you would need to know a bunch of values I'm not sure where you would get. Transistor model parameters, trace capacitances and resistances, etc, etc. Do you have access to these values? I also have not heard of analog simulations of entire processors, I'd imagine it would be incredibly slow. Maybe simulate one module at a time.
– serpixo
Jan 2 at 22:36
add a comment |
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1 Answer
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1 Answer
1
active
oldest
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active
oldest
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active
oldest
votes
There is no concept of analog values such as voltage in verilog or VHDL. Just digital signals and simple timing.
Analog simulations are done in other languages like SPICE.
answered Dec 28 '18 at 23:24
serpixoserpixo
1236
Thank you for your answer. Can we change analog values after synthesis and getting gate level netlist?
– deadpool3
Jan 2 at 21:36
This is out of my expertise, so I'm not sure. It may be possible to export from a gate level netlist to spice netlist, but you would need to know a bunch of values I'm not sure where you would get. Transistor model parameters, trace capacitances and resistances, etc, etc. Do you have access to these values? I also have not heard of analog simulations of entire processors, I'd imagine it would be incredibly slow. Maybe simulate one module at a time.
– serpixo
Jan 2 at 22:36
add a comment |
There is no concept of analog values such as voltage in verilog or VHDL. Just digital signals and simple timing.
Analog simulations are done in other languages like SPICE.
answered Dec 28 '18 at 23:24
serpixoserpixo
1236
Thank you for your answer. Can we change analog values after synthesis and getting gate level netlist?
– deadpool3
Jan 2 at 21:36
This is out of my expertise, so I'm not sure. It may be possible to export from a gate level netlist to spice netlist, but you would need to know a bunch of values I'm not sure where you would get. Transistor model parameters, trace capacitances and resistances, etc, etc. Do you have access to these values? I also have not heard of analog simulations of entire processors, I'd imagine it would be incredibly slow. Maybe simulate one module at a time.
– serpixo
Jan 2 at 22:36
add a comment |
There is no concept of analog values such as voltage in verilog or VHDL. Just digital signals and simple timing.
Analog simulations are done in other languages like SPICE.
answered Dec 28 '18 at 23:24
serpixoserpixo
1236
There is no concept of analog values such as voltage in verilog or VHDL. Just digital signals and simple timing.
Analog simulations are done in other languages like SPICE.
answered Dec 28 '18 at 23:24
serpixoserpixo
1236
answered Dec 28 '18 at 23:24
serpixoserpixo
1236
answered Dec 28 '18 at 23:24
serpixoserpixo
1236
answered Dec 28 '18 at 23:24
serpixoserpixo
1236
1236
Thank you for your answer. Can we change analog values after synthesis and getting gate level netlist?
– deadpool3
Jan 2 at 21:36
This is out of my expertise, so I'm not sure. It may be possible to export from a gate level netlist to spice netlist, but you would need to know a bunch of values I'm not sure where you would get. Transistor model parameters, trace capacitances and resistances, etc, etc. Do you have access to these values? I also have not heard of analog simulations of entire processors, I'd imagine it would be incredibly slow. Maybe simulate one module at a time.
– serpixo
Jan 2 at 22:36
add a comment |
Thank you for your answer. Can we change analog values after synthesis and getting gate level netlist?
– deadpool3
Jan 2 at 21:36
This is out of my expertise, so I'm not sure. It may be possible to export from a gate level netlist to spice netlist, but you would need to know a bunch of values I'm not sure where you would get. Transistor model parameters, trace capacitances and resistances, etc, etc. Do you have access to these values? I also have not heard of analog simulations of entire processors, I'd imagine it would be incredibly slow. Maybe simulate one module at a time.
– serpixo
Jan 2 at 22:36
Thank you for your answer. Can we change analog values after synthesis and getting gate level netlist?
– deadpool3
Jan 2 at 21:36
Thank you for your answer. Can we change analog values after synthesis and getting gate level netlist?
– deadpool3
Jan 2 at 21:36
This is out of my expertise, so I'm not sure. It may be possible to export from a gate level netlist to spice netlist, but you would need to know a bunch of values I'm not sure where you would get. Transistor model parameters, trace capacitances and resistances, etc, etc. Do you have access to these values? I also have not heard of analog simulations of entire processors, I'd imagine it would be incredibly slow. Maybe simulate one module at a time.
– serpixo
Jan 2 at 22:36
This is out of my expertise, so I'm not sure. It may be possible to export from a gate level netlist to spice netlist, but you would need to know a bunch of values I'm not sure where you would get. Transistor model parameters, trace capacitances and resistances, etc, etc. Do you have access to these values? I also have not heard of analog simulations of entire processors, I'd imagine it would be incredibly slow. Maybe simulate one module at a time.
– serpixo
Jan 2 at 22:36
add a comment |
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