Delay associated with xor of 1023 10 bit vectors in Verilog
I am somewhat new to verilog and I have a question that is confusing me .
I have a number of constant parameters , specifically nearly 1023 of them c0 , c1,c2 ..... c1022, each one being 10 bit in length . I also have a vector r[1022:0] , which is 1023 bits in length . My task is to compute ci*r[i] where i varies from 0 to 1022 and finally take the xor of the 1023 10 bit vectors that i get.When I do this in simulation , verilog generates the output at time 0 for the assign statement . How can verilog generate the output at time 0 ? Will there be no delay associated with these 1023 xors?
Also, if I need to do this succinctly , is there a short form that I can use or do I need to manually write c0 *r[0] ^ c1 *r[1] ......^ c[1022]*r[1022] which is synthesizable ?
verilog fpga
asked Jan 3 at 2:18
Sushrut KaulSushrut Kaul
204
add a comment |
I am somewhat new to verilog and I have a question that is confusing me .
I have a number of constant parameters , specifically nearly 1023 of them c0 , c1,c2 ..... c1022, each one being 10 bit in length . I also have a vector r[1022:0] , which is 1023 bits in length . My task is to compute ci*r[i] where i varies from 0 to 1022 and finally take the xor of the 1023 10 bit vectors that i get.When I do this in simulation , verilog generates the output at time 0 for the assign statement . How can verilog generate the output at time 0 ? Will there be no delay associated with these 1023 xors?
Also, if I need to do this succinctly , is there a short form that I can use or do I need to manually write c0 *r[0] ^ c1 *r[1] ......^ c[1022]*r[1022] which is synthesizable ?
verilog fpga
asked Jan 3 at 2:18
Sushrut KaulSushrut Kaul
204
Probably you're doing functional simulation, while you should be doing timing simulation to see the delay you mentioned.
– Qiu
Jan 3 at 6:45
add a comment |
I am somewhat new to verilog and I have a question that is confusing me .
I have a number of constant parameters , specifically nearly 1023 of them c0 , c1,c2 ..... c1022, each one being 10 bit in length . I also have a vector r[1022:0] , which is 1023 bits in length . My task is to compute ci*r[i] where i varies from 0 to 1022 and finally take the xor of the 1023 10 bit vectors that i get.When I do this in simulation , verilog generates the output at time 0 for the assign statement . How can verilog generate the output at time 0 ? Will there be no delay associated with these 1023 xors?
Also, if I need to do this succinctly , is there a short form that I can use or do I need to manually write c0 *r[0] ^ c1 *r[1] ......^ c[1022]*r[1022] which is synthesizable ?
verilog fpga
asked Jan 3 at 2:18
Sushrut KaulSushrut Kaul
204
I am somewhat new to verilog and I have a question that is confusing me .
I have a number of constant parameters , specifically nearly 1023 of them c0 , c1,c2 ..... c1022, each one being 10 bit in length . I also have a vector r[1022:0] , which is 1023 bits in length . My task is to compute ci*r[i] where i varies from 0 to 1022 and finally take the xor of the 1023 10 bit vectors that i get.When I do this in simulation , verilog generates the output at time 0 for the assign statement . How can verilog generate the output at time 0 ? Will there be no delay associated with these 1023 xors?
Also, if I need to do this succinctly , is there a short form that I can use or do I need to manually write c0 *r[0] ^ c1 *r[1] ......^ c[1022]*r[1022] which is synthesizable ?
verilog fpga
verilog fpga
asked Jan 3 at 2:18
Sushrut KaulSushrut Kaul
204
asked Jan 3 at 2:18
Sushrut KaulSushrut Kaul
204
asked Jan 3 at 2:18
Sushrut KaulSushrut Kaul
204
asked Jan 3 at 2:18
Sushrut KaulSushrut Kaul
204
asked Jan 3 at 2:18
Sushrut KaulSushrut Kaul
204
204
Probably you're doing functional simulation, while you should be doing timing simulation to see the delay you mentioned.
– Qiu
Jan 3 at 6:45
add a comment |
Probably you're doing functional simulation, while you should be doing timing simulation to see the delay you mentioned.
– Qiu
Jan 3 at 6:45
Probably you're doing functional simulation, while you should be doing timing simulation to see the delay you mentioned.
– Qiu
Jan 3 at 6:45
Probably you're doing functional simulation, while you should be doing timing simulation to see the delay you mentioned.
– Qiu
Jan 3 at 6:45
add a comment |
1 Answer
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A Verilog simulator will execute whatever legal syntax you give it—the tool knows nothing about what the implementation eventually looks like. It's up to you to feed timing constraints to the synthesis tool and it tells you if it can fit the logic to meet the constraints (or you might have to run another tool to see if it meets timing constraints).
Since you named your parameters c0, c1, c2, ..., you might as well named them czero, cone, ctwo, ... which gives you no options for shortcuts.
If you tool supports SystemVerilog, you can write your parameter as an array and then use the array xor reduction operator
parameter [9:0] C[1023] = {10'h123, 10'h234, ...};
assign out = C.xor() with (item*r[item.index]);
If you synthesis tool does not support this SystemVerilog syntax you, you can pack the parameter values into a single vector and use an indexed part select in Verilog.
parameter [10220-1:0] C = {10'h123, 10'h234, ...};
function [9:0] xor_reduction (input [1022:0] r);
integer I;
begin
xor_reduction = 0;
for(I=0;I<1023;I=I+1)
xor_reduction = xor_refuction ^ (r[1022-I]*C[I-:10]);
end
endfunction
assign out = xor_reduction(r);
answered Jan 3 at 6:46
dave_59dave_59
20.6k21638
1
Addendum to dave_59's answer: If after synthesis you design fails timing, you should then look into make the design pipe-lined by adding register stages. Your problem is extremely well suited for that as the data-flow is all in 'one direction'. You latency will increase but the logic should be able to run at very, very high clock speeds.
– Oldfart
Jan 3 at 13:45
Thanks a lot !!!!
– Sushrut Kaul
Jan 3 at 16:32
add a comment |
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A Verilog simulator will execute whatever legal syntax you give it—the tool knows nothing about what the implementation eventually looks like. It's up to you to feed timing constraints to the synthesis tool and it tells you if it can fit the logic to meet the constraints (or you might have to run another tool to see if it meets timing constraints).
Since you named your parameters c0, c1, c2, ..., you might as well named them czero, cone, ctwo, ... which gives you no options for shortcuts.
If you tool supports SystemVerilog, you can write your parameter as an array and then use the array xor reduction operator
parameter [9:0] C[1023] = {10'h123, 10'h234, ...};
assign out = C.xor() with (item*r[item.index]);
If you synthesis tool does not support this SystemVerilog syntax you, you can pack the parameter values into a single vector and use an indexed part select in Verilog.
parameter [10220-1:0] C = {10'h123, 10'h234, ...};
function [9:0] xor_reduction (input [1022:0] r);
integer I;
begin
xor_reduction = 0;
for(I=0;I<1023;I=I+1)
xor_reduction = xor_refuction ^ (r[1022-I]*C[I-:10]);
end
endfunction
assign out = xor_reduction(r);
answered Jan 3 at 6:46
dave_59dave_59
20.6k21638
1
Addendum to dave_59's answer: If after synthesis you design fails timing, you should then look into make the design pipe-lined by adding register stages. Your problem is extremely well suited for that as the data-flow is all in 'one direction'. You latency will increase but the logic should be able to run at very, very high clock speeds.
– Oldfart
Jan 3 at 13:45
Thanks a lot !!!!
– Sushrut Kaul
Jan 3 at 16:32
add a comment |
A Verilog simulator will execute whatever legal syntax you give it—the tool knows nothing about what the implementation eventually looks like. It's up to you to feed timing constraints to the synthesis tool and it tells you if it can fit the logic to meet the constraints (or you might have to run another tool to see if it meets timing constraints).
Since you named your parameters c0, c1, c2, ..., you might as well named them czero, cone, ctwo, ... which gives you no options for shortcuts.
If you tool supports SystemVerilog, you can write your parameter as an array and then use the array xor reduction operator
parameter [9:0] C[1023] = {10'h123, 10'h234, ...};
assign out = C.xor() with (item*r[item.index]);
If you synthesis tool does not support this SystemVerilog syntax you, you can pack the parameter values into a single vector and use an indexed part select in Verilog.
parameter [10220-1:0] C = {10'h123, 10'h234, ...};
function [9:0] xor_reduction (input [1022:0] r);
integer I;
begin
xor_reduction = 0;
for(I=0;I<1023;I=I+1)
xor_reduction = xor_refuction ^ (r[1022-I]*C[I-:10]);
end
endfunction
assign out = xor_reduction(r);
answered Jan 3 at 6:46
dave_59dave_59
20.6k21638
1
Addendum to dave_59's answer: If after synthesis you design fails timing, you should then look into make the design pipe-lined by adding register stages. Your problem is extremely well suited for that as the data-flow is all in 'one direction'. You latency will increase but the logic should be able to run at very, very high clock speeds.
– Oldfart
Jan 3 at 13:45
Thanks a lot !!!!
– Sushrut Kaul
Jan 3 at 16:32
add a comment |
A Verilog simulator will execute whatever legal syntax you give it—the tool knows nothing about what the implementation eventually looks like. It's up to you to feed timing constraints to the synthesis tool and it tells you if it can fit the logic to meet the constraints (or you might have to run another tool to see if it meets timing constraints).
Since you named your parameters c0, c1, c2, ..., you might as well named them czero, cone, ctwo, ... which gives you no options for shortcuts.
If you tool supports SystemVerilog, you can write your parameter as an array and then use the array xor reduction operator
parameter [9:0] C[1023] = {10'h123, 10'h234, ...};
assign out = C.xor() with (item*r[item.index]);
If you synthesis tool does not support this SystemVerilog syntax you, you can pack the parameter values into a single vector and use an indexed part select in Verilog.
parameter [10220-1:0] C = {10'h123, 10'h234, ...};
function [9:0] xor_reduction (input [1022:0] r);
integer I;
begin
xor_reduction = 0;
for(I=0;I<1023;I=I+1)
xor_reduction = xor_refuction ^ (r[1022-I]*C[I-:10]);
end
endfunction
assign out = xor_reduction(r);
answered Jan 3 at 6:46
dave_59dave_59
20.6k21638
A Verilog simulator will execute whatever legal syntax you give it—the tool knows nothing about what the implementation eventually looks like. It's up to you to feed timing constraints to the synthesis tool and it tells you if it can fit the logic to meet the constraints (or you might have to run another tool to see if it meets timing constraints).
Since you named your parameters c0, c1, c2, ..., you might as well named them czero, cone, ctwo, ... which gives you no options for shortcuts.
If you tool supports SystemVerilog, you can write your parameter as an array and then use the array xor reduction operator
parameter [9:0] C[1023] = {10'h123, 10'h234, ...};
assign out = C.xor() with (item*r[item.index]);
If you synthesis tool does not support this SystemVerilog syntax you, you can pack the parameter values into a single vector and use an indexed part select in Verilog.
parameter [10220-1:0] C = {10'h123, 10'h234, ...};
function [9:0] xor_reduction (input [1022:0] r);
integer I;
begin
xor_reduction = 0;
for(I=0;I<1023;I=I+1)
xor_reduction = xor_refuction ^ (r[1022-I]*C[I-:10]);
end
endfunction
assign out = xor_reduction(r);
answered Jan 3 at 6:46
dave_59dave_59
20.6k21638
edited Jan 3 at 6:59
answered Jan 3 at 6:46
dave_59dave_59
20.6k21638
answered Jan 3 at 6:46
dave_59dave_59
20.6k21638
answered Jan 3 at 6:46
dave_59dave_59
20.6k21638
20.6k21638
1
Addendum to dave_59's answer: If after synthesis you design fails timing, you should then look into make the design pipe-lined by adding register stages. Your problem is extremely well suited for that as the data-flow is all in 'one direction'. You latency will increase but the logic should be able to run at very, very high clock speeds.
– Oldfart
Jan 3 at 13:45
Thanks a lot !!!!
– Sushrut Kaul
Jan 3 at 16:32
add a comment |
1
Addendum to dave_59's answer: If after synthesis you design fails timing, you should then look into make the design pipe-lined by adding register stages. Your problem is extremely well suited for that as the data-flow is all in 'one direction'. You latency will increase but the logic should be able to run at very, very high clock speeds.
– Oldfart
Jan 3 at 13:45
Thanks a lot !!!!
– Sushrut Kaul
Jan 3 at 16:32
1
1
Addendum to dave_59's answer: If after synthesis you design fails timing, you should then look into make the design pipe-lined by adding register stages. Your problem is extremely well suited for that as the data-flow is all in 'one direction'. You latency will increase but the logic should be able to run at very, very high clock speeds.
– Oldfart
Jan 3 at 13:45
Addendum to dave_59's answer: If after synthesis you design fails timing, you should then look into make the design pipe-lined by adding register stages. Your problem is extremely well suited for that as the data-flow is all in 'one direction'. You latency will increase but the logic should be able to run at very, very high clock speeds.
– Oldfart
Jan 3 at 13:45
Thanks a lot !!!!
– Sushrut Kaul
Jan 3 at 16:32
Thanks a lot !!!!
– Sushrut Kaul
Jan 3 at 16:32
add a comment |
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Probably you're doing functional simulation, while you should be doing timing simulation to see the delay you mentioned.
– Qiu
Jan 3 at 6:45