aarch64; Load-Acquire Exclusive vs Load Exclusive
What is the difference between LDAXR & LDXR instructions out of AArch64 instruction set?
From reference manual they looks totally the same (with exception of 'acquire' word):
LDAXR - Load-Acquire Exclusive Register: loads word from memory addressed by base to Wt. Records the physical address as an exclusive access.
LDXR - Load Exclusive Register: loads a word from memory addressed by base to Wt. Records the physical address as an exclusive access.
Thanks
arm locking arm64
asked Jan 3 at 1:50
user3124812user3124812
4241517
add a comment |
What is the difference between LDAXR & LDXR instructions out of AArch64 instruction set?
From reference manual they looks totally the same (with exception of 'acquire' word):
LDAXR - Load-Acquire Exclusive Register: loads word from memory addressed by base to Wt. Records the physical address as an exclusive access.
LDXR - Load Exclusive Register: loads a word from memory addressed by base to Wt. Records the physical address as an exclusive access.
Thanks
arm locking arm64
asked Jan 3 at 1:50
user3124812user3124812
4241517
1
Please provide a reference to your 'reference manual', since I see something different in version D of the ARMv8 ARM.
– Sean Houlihane
Jan 3 at 9:14
1
that's out of "ARMv8 Instruction Set Overview"
– user3124812
Jan 3 at 23:40
add a comment |
What is the difference between LDAXR & LDXR instructions out of AArch64 instruction set?
From reference manual they looks totally the same (with exception of 'acquire' word):
LDAXR - Load-Acquire Exclusive Register: loads word from memory addressed by base to Wt. Records the physical address as an exclusive access.
LDXR - Load Exclusive Register: loads a word from memory addressed by base to Wt. Records the physical address as an exclusive access.
Thanks
arm locking arm64
asked Jan 3 at 1:50
user3124812user3124812
4241517
What is the difference between LDAXR & LDXR instructions out of AArch64 instruction set?
From reference manual they looks totally the same (with exception of 'acquire' word):
LDAXR - Load-Acquire Exclusive Register: loads word from memory addressed by base to Wt. Records the physical address as an exclusive access.
LDXR - Load Exclusive Register: loads a word from memory addressed by base to Wt. Records the physical address as an exclusive access.
Thanks
arm locking arm64
arm locking arm64
asked Jan 3 at 1:50
user3124812user3124812
4241517
asked Jan 3 at 1:50
user3124812user3124812
4241517
asked Jan 3 at 1:50
user3124812user3124812
4241517
asked Jan 3 at 1:50
user3124812user3124812
4241517
asked Jan 3 at 1:50
user3124812user3124812
4241517
4241517
1
Please provide a reference to your 'reference manual', since I see something different in version D of the ARMv8 ARM.
– Sean Houlihane
Jan 3 at 9:14
1
that's out of "ARMv8 Instruction Set Overview"
– user3124812
Jan 3 at 23:40
add a comment |
1
Please provide a reference to your 'reference manual', since I see something different in version D of the ARMv8 ARM.
– Sean Houlihane
Jan 3 at 9:14
1
that's out of "ARMv8 Instruction Set Overview"
– user3124812
Jan 3 at 23:40
1
1
Please provide a reference to your 'reference manual', since I see something different in version D of the ARMv8 ARM.
– Sean Houlihane
Jan 3 at 9:14
Please provide a reference to your 'reference manual', since I see something different in version D of the ARMv8 ARM.
– Sean Houlihane
Jan 3 at 9:14
1
1
that's out of "ARMv8 Instruction Set Overview"
– user3124812
Jan 3 at 23:40
that's out of "ARMv8 Instruction Set Overview"
– user3124812
Jan 3 at 23:40
add a comment |
1 Answer
1
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oldest
votes
In the simplest form, LDAEX == LDXR +DMB_SY.
This is the description which I find for LDAXR:
C6.2.104 LDAXR
Load-Acquire Exclusive Register derives an address from a base
register value, loads a 32-bit word or 64-bit doubleword from memory,
and writes it to a register. The memory access is atomic. The PE marks
the physical address being accessed as an exclusive access. This
exclusive access mark is checked by Store Exclusive instructions. See
Synchronization and semaphores on page B2-135. The instruction also
has memory ordering semantics as described in Load-Acquire,
Load-AcquirePC, and Store-Release on page B2-108. For information
about memory accesses see Load/Store addressing modes on page C1-157.
From section K11.3 of DDI0487 Da
The ARMv8 architecture adds the acquire and release semantics to
Load-Exclusive and Store-Exclusive instructions, which allows them to
gain ordering acquire and/or release semantics. The Load-Exclusive
instruction can be specified to have acquire semantics, and the
Store-Exclusive instruction can be specified to have release
semantics. These can be arbitrarily combined to allow the atomic
update created by a successful Load-Exclusive and Store-Exclusive pair
to have any of:
No Ordering semantics (using LDREX and STREX).
Acquire only semantics (using LDAEX and STREX).
Release only semantics (using LDREX and STLEX).
Sequentially consistent semantics (using LDAEX and STLEX).
Also (B2.3.5),
The basic principle of a Load-Acquire instruction is to introduce
order between the memory access generated by the Load-Acquire
instruction and the memory accesses appearing in program order after
the Load-Acquire instruction, such that the memory access generated by
the Load-Acquire instruction is Observed-by each PE, to the extent
that that PE is required to observe the access coherently, before any
of the memory accesses appearing in program order after the
Load-Acquire instruction are Observed-by that PE, to the extent that
the PE is required to observe the accesses coherently.
answered Jan 3 at 9:12
Sean HoulihaneSean Houlihane
8011118
Thanks, I searched by an instruction mnemonic and missed that part.
– user3124812
Jan 3 at 23:44
1
So just to summarise, that's only about memory ordering and simply speakingLDAEX==LDXR + DMB_SY
– user3124812
Jan 3 at 23:46
add a comment |
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In the simplest form, LDAEX == LDXR +DMB_SY.
This is the description which I find for LDAXR:
C6.2.104 LDAXR
Load-Acquire Exclusive Register derives an address from a base
register value, loads a 32-bit word or 64-bit doubleword from memory,
and writes it to a register. The memory access is atomic. The PE marks
the physical address being accessed as an exclusive access. This
exclusive access mark is checked by Store Exclusive instructions. See
Synchronization and semaphores on page B2-135. The instruction also
has memory ordering semantics as described in Load-Acquire,
Load-AcquirePC, and Store-Release on page B2-108. For information
about memory accesses see Load/Store addressing modes on page C1-157.
From section K11.3 of DDI0487 Da
The ARMv8 architecture adds the acquire and release semantics to
Load-Exclusive and Store-Exclusive instructions, which allows them to
gain ordering acquire and/or release semantics. The Load-Exclusive
instruction can be specified to have acquire semantics, and the
Store-Exclusive instruction can be specified to have release
semantics. These can be arbitrarily combined to allow the atomic
update created by a successful Load-Exclusive and Store-Exclusive pair
to have any of:
No Ordering semantics (using LDREX and STREX).
Acquire only semantics (using LDAEX and STREX).
Release only semantics (using LDREX and STLEX).
Sequentially consistent semantics (using LDAEX and STLEX).
Also (B2.3.5),
The basic principle of a Load-Acquire instruction is to introduce
order between the memory access generated by the Load-Acquire
instruction and the memory accesses appearing in program order after
the Load-Acquire instruction, such that the memory access generated by
the Load-Acquire instruction is Observed-by each PE, to the extent
that that PE is required to observe the access coherently, before any
of the memory accesses appearing in program order after the
Load-Acquire instruction are Observed-by that PE, to the extent that
the PE is required to observe the accesses coherently.
answered Jan 3 at 9:12
Sean HoulihaneSean Houlihane
8011118
Thanks, I searched by an instruction mnemonic and missed that part.
– user3124812
Jan 3 at 23:44
1
So just to summarise, that's only about memory ordering and simply speakingLDAEX==LDXR + DMB_SY
– user3124812
Jan 3 at 23:46
add a comment |
In the simplest form, LDAEX == LDXR +DMB_SY.
This is the description which I find for LDAXR:
C6.2.104 LDAXR
Load-Acquire Exclusive Register derives an address from a base
register value, loads a 32-bit word or 64-bit doubleword from memory,
and writes it to a register. The memory access is atomic. The PE marks
the physical address being accessed as an exclusive access. This
exclusive access mark is checked by Store Exclusive instructions. See
Synchronization and semaphores on page B2-135. The instruction also
has memory ordering semantics as described in Load-Acquire,
Load-AcquirePC, and Store-Release on page B2-108. For information
about memory accesses see Load/Store addressing modes on page C1-157.
From section K11.3 of DDI0487 Da
The ARMv8 architecture adds the acquire and release semantics to
Load-Exclusive and Store-Exclusive instructions, which allows them to
gain ordering acquire and/or release semantics. The Load-Exclusive
instruction can be specified to have acquire semantics, and the
Store-Exclusive instruction can be specified to have release
semantics. These can be arbitrarily combined to allow the atomic
update created by a successful Load-Exclusive and Store-Exclusive pair
to have any of:
No Ordering semantics (using LDREX and STREX).
Acquire only semantics (using LDAEX and STREX).
Release only semantics (using LDREX and STLEX).
Sequentially consistent semantics (using LDAEX and STLEX).
Also (B2.3.5),
The basic principle of a Load-Acquire instruction is to introduce
order between the memory access generated by the Load-Acquire
instruction and the memory accesses appearing in program order after
the Load-Acquire instruction, such that the memory access generated by
the Load-Acquire instruction is Observed-by each PE, to the extent
that that PE is required to observe the access coherently, before any
of the memory accesses appearing in program order after the
Load-Acquire instruction are Observed-by that PE, to the extent that
the PE is required to observe the accesses coherently.
answered Jan 3 at 9:12
Sean HoulihaneSean Houlihane
8011118
Thanks, I searched by an instruction mnemonic and missed that part.
– user3124812
Jan 3 at 23:44
1
So just to summarise, that's only about memory ordering and simply speakingLDAEX==LDXR + DMB_SY
– user3124812
Jan 3 at 23:46
add a comment |
In the simplest form, LDAEX == LDXR +DMB_SY.
This is the description which I find for LDAXR:
C6.2.104 LDAXR
Load-Acquire Exclusive Register derives an address from a base
register value, loads a 32-bit word or 64-bit doubleword from memory,
and writes it to a register. The memory access is atomic. The PE marks
the physical address being accessed as an exclusive access. This
exclusive access mark is checked by Store Exclusive instructions. See
Synchronization and semaphores on page B2-135. The instruction also
has memory ordering semantics as described in Load-Acquire,
Load-AcquirePC, and Store-Release on page B2-108. For information
about memory accesses see Load/Store addressing modes on page C1-157.
From section K11.3 of DDI0487 Da
The ARMv8 architecture adds the acquire and release semantics to
Load-Exclusive and Store-Exclusive instructions, which allows them to
gain ordering acquire and/or release semantics. The Load-Exclusive
instruction can be specified to have acquire semantics, and the
Store-Exclusive instruction can be specified to have release
semantics. These can be arbitrarily combined to allow the atomic
update created by a successful Load-Exclusive and Store-Exclusive pair
to have any of:
No Ordering semantics (using LDREX and STREX).
Acquire only semantics (using LDAEX and STREX).
Release only semantics (using LDREX and STLEX).
Sequentially consistent semantics (using LDAEX and STLEX).
Also (B2.3.5),
The basic principle of a Load-Acquire instruction is to introduce
order between the memory access generated by the Load-Acquire
instruction and the memory accesses appearing in program order after
the Load-Acquire instruction, such that the memory access generated by
the Load-Acquire instruction is Observed-by each PE, to the extent
that that PE is required to observe the access coherently, before any
of the memory accesses appearing in program order after the
Load-Acquire instruction are Observed-by that PE, to the extent that
the PE is required to observe the accesses coherently.
answered Jan 3 at 9:12
Sean HoulihaneSean Houlihane
8011118
In the simplest form, LDAEX == LDXR +DMB_SY.
This is the description which I find for LDAXR:
C6.2.104 LDAXR
Load-Acquire Exclusive Register derives an address from a base
register value, loads a 32-bit word or 64-bit doubleword from memory,
and writes it to a register. The memory access is atomic. The PE marks
the physical address being accessed as an exclusive access. This
exclusive access mark is checked by Store Exclusive instructions. See
Synchronization and semaphores on page B2-135. The instruction also
has memory ordering semantics as described in Load-Acquire,
Load-AcquirePC, and Store-Release on page B2-108. For information
about memory accesses see Load/Store addressing modes on page C1-157.
From section K11.3 of DDI0487 Da
The ARMv8 architecture adds the acquire and release semantics to
Load-Exclusive and Store-Exclusive instructions, which allows them to
gain ordering acquire and/or release semantics. The Load-Exclusive
instruction can be specified to have acquire semantics, and the
Store-Exclusive instruction can be specified to have release
semantics. These can be arbitrarily combined to allow the atomic
update created by a successful Load-Exclusive and Store-Exclusive pair
to have any of:
No Ordering semantics (using LDREX and STREX).
Acquire only semantics (using LDAEX and STREX).
Release only semantics (using LDREX and STLEX).
Sequentially consistent semantics (using LDAEX and STLEX).
Also (B2.3.5),
The basic principle of a Load-Acquire instruction is to introduce
order between the memory access generated by the Load-Acquire
instruction and the memory accesses appearing in program order after
the Load-Acquire instruction, such that the memory access generated by
the Load-Acquire instruction is Observed-by each PE, to the extent
that that PE is required to observe the access coherently, before any
of the memory accesses appearing in program order after the
Load-Acquire instruction are Observed-by that PE, to the extent that
the PE is required to observe the accesses coherently.
answered Jan 3 at 9:12
Sean HoulihaneSean Houlihane
8011118
edited Jan 4 at 8:52
answered Jan 3 at 9:12
Sean HoulihaneSean Houlihane
8011118
answered Jan 3 at 9:12
Sean HoulihaneSean Houlihane
8011118
answered Jan 3 at 9:12
Sean HoulihaneSean Houlihane
8011118
8011118
Thanks, I searched by an instruction mnemonic and missed that part.
– user3124812
Jan 3 at 23:44
1
So just to summarise, that's only about memory ordering and simply speakingLDAEX==LDXR + DMB_SY
– user3124812
Jan 3 at 23:46
add a comment |
Thanks, I searched by an instruction mnemonic and missed that part.
– user3124812
Jan 3 at 23:44
1
So just to summarise, that's only about memory ordering and simply speakingLDAEX==LDXR + DMB_SY
– user3124812
Jan 3 at 23:46
Thanks, I searched by an instruction mnemonic and missed that part.
– user3124812
Jan 3 at 23:44
Thanks, I searched by an instruction mnemonic and missed that part.
– user3124812
Jan 3 at 23:44
1
1
So just to summarise, that's only about memory ordering and simply speaking
LDAEX == LDXR + DMB_SY– user3124812
Jan 3 at 23:46
So just to summarise, that's only about memory ordering and simply speaking
LDAEX == LDXR + DMB_SY– user3124812
Jan 3 at 23:46
add a comment |
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1
Please provide a reference to your 'reference manual', since I see something different in version D of the ARMv8 ARM.
– Sean Houlihane
Jan 3 at 9:14
1
that's out of "ARMv8 Instruction Set Overview"
– user3124812
Jan 3 at 23:40