Can I modify a signal within a process if it's also in the sensitivity list in VHDL?
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I understand that changes to a signal within a process would take place at the end of the process.
I need the process to modify signals that are in it's sensitivity list and then reevaluate;
something like
signal a: std_logic;
signal b: std_logic;
process(a,b) begin
if(b='1') then
a<='0';
end if;
end process;
vhdl vivado
asked Jan 3 at 23:54
Florea VladFlorea Vlad
43
add a comment |
0
I understand that changes to a signal within a process would take place at the end of the process.
I need the process to modify signals that are in it's sensitivity list and then reevaluate;
something like
signal a: std_logic;
signal b: std_logic;
process(a,b) begin
if(b='1') then
a<='0';
end if;
end process;
vhdl vivado
asked Jan 3 at 23:54
Florea VladFlorea Vlad
43
1
Yes. Your yes/no question snippet doesn't have the structure described in the title. See IEEE Std 1076-2008 10.2 Wait statement for the rules for constructing a sensitivity list. In -2008 you can use the reserved wordallto construct the sensitivity list from every signal evaluated in any process statement. Your snippet doesn't evaluate a. You'd get the process to resume needlessly once every time a is assigned and a is already '0'. An assignment schedules an update, if the value changes you get an event (14.7.3.4 Signal update) and the process resumes (14.7.5.3 Simulation cycle).
– user1155120
Jan 4 at 0:46
You are probably looking for a variable in a process. Variables are updated immediately, but not at the next wait statement. Please not a process with sensitivity ist is equivalent to a process with await on <signallist>;before theend process;
– Paebbels
Jan 4 at 7:20
If you update a signal in the sensitivity list, you will cause the process to be re-evaluated. It is possible to cause an infinite loop like this and cause a simulator to hit the iteration limit (and fail) or create a logic loop in real hardware.
– Tricky
Jan 4 at 9:17
Thank you, I understand now :)
– Florea Vlad
Jan 4 at 12:47
add a comment |
0
0
0
I understand that changes to a signal within a process would take place at the end of the process.
I need the process to modify signals that are in it's sensitivity list and then reevaluate;
something like
signal a: std_logic;
signal b: std_logic;
process(a,b) begin
if(b='1') then
a<='0';
end if;
end process;
vhdl vivado
asked Jan 3 at 23:54
Florea VladFlorea Vlad
43
I understand that changes to a signal within a process would take place at the end of the process.
I need the process to modify signals that are in it's sensitivity list and then reevaluate;
something like
signal a: std_logic;
signal b: std_logic;
process(a,b) begin
if(b='1') then
a<='0';
end if;
end process;
vhdl vivado
vhdl vivado
asked Jan 3 at 23:54
Florea VladFlorea Vlad
43
asked Jan 3 at 23:54
Florea VladFlorea Vlad
43
asked Jan 3 at 23:54
Florea VladFlorea Vlad
43
asked Jan 3 at 23:54
Florea VladFlorea Vlad
43
asked Jan 3 at 23:54
Florea VladFlorea Vlad
43
43
1
Yes. Your yes/no question snippet doesn't have the structure described in the title. See IEEE Std 1076-2008 10.2 Wait statement for the rules for constructing a sensitivity list. In -2008 you can use the reserved wordallto construct the sensitivity list from every signal evaluated in any process statement. Your snippet doesn't evaluate a. You'd get the process to resume needlessly once every time a is assigned and a is already '0'. An assignment schedules an update, if the value changes you get an event (14.7.3.4 Signal update) and the process resumes (14.7.5.3 Simulation cycle).
– user1155120
Jan 4 at 0:46
You are probably looking for a variable in a process. Variables are updated immediately, but not at the next wait statement. Please not a process with sensitivity ist is equivalent to a process with await on <signallist>;before theend process;
– Paebbels
Jan 4 at 7:20
If you update a signal in the sensitivity list, you will cause the process to be re-evaluated. It is possible to cause an infinite loop like this and cause a simulator to hit the iteration limit (and fail) or create a logic loop in real hardware.
– Tricky
Jan 4 at 9:17
Thank you, I understand now :)
– Florea Vlad
Jan 4 at 12:47
add a comment |
1
Yes. Your yes/no question snippet doesn't have the structure described in the title. See IEEE Std 1076-2008 10.2 Wait statement for the rules for constructing a sensitivity list. In -2008 you can use the reserved wordallto construct the sensitivity list from every signal evaluated in any process statement. Your snippet doesn't evaluate a. You'd get the process to resume needlessly once every time a is assigned and a is already '0'. An assignment schedules an update, if the value changes you get an event (14.7.3.4 Signal update) and the process resumes (14.7.5.3 Simulation cycle).
– user1155120
Jan 4 at 0:46
You are probably looking for a variable in a process. Variables are updated immediately, but not at the next wait statement. Please not a process with sensitivity ist is equivalent to a process with await on <signallist>;before theend process;
– Paebbels
Jan 4 at 7:20
If you update a signal in the sensitivity list, you will cause the process to be re-evaluated. It is possible to cause an infinite loop like this and cause a simulator to hit the iteration limit (and fail) or create a logic loop in real hardware.
– Tricky
Jan 4 at 9:17
Thank you, I understand now :)
– Florea Vlad
Jan 4 at 12:47
1
1
Yes. Your yes/no question snippet doesn't have the structure described in the title. See IEEE Std 1076-2008 10.2 Wait statement for the rules for constructing a sensitivity list. In -2008 you can use the reserved word
all to construct the sensitivity list from every signal evaluated in any process statement. Your snippet doesn't evaluate a. You'd get the process to resume needlessly once every time a is assigned and a is already '0'. An assignment schedules an update, if the value changes you get an event (14.7.3.4 Signal update) and the process resumes (14.7.5.3 Simulation cycle).– user1155120
Jan 4 at 0:46
Yes. Your yes/no question snippet doesn't have the structure described in the title. See IEEE Std 1076-2008 10.2 Wait statement for the rules for constructing a sensitivity list. In -2008 you can use the reserved word
all to construct the sensitivity list from every signal evaluated in any process statement. Your snippet doesn't evaluate a. You'd get the process to resume needlessly once every time a is assigned and a is already '0'. An assignment schedules an update, if the value changes you get an event (14.7.3.4 Signal update) and the process resumes (14.7.5.3 Simulation cycle).– user1155120
Jan 4 at 0:46
You are probably looking for a variable in a process. Variables are updated immediately, but not at the next wait statement. Please not a process with sensitivity ist is equivalent to a process with a
wait on <signallist>; before the end process;– Paebbels
Jan 4 at 7:20
You are probably looking for a variable in a process. Variables are updated immediately, but not at the next wait statement. Please not a process with sensitivity ist is equivalent to a process with a
wait on <signallist>; before the end process;– Paebbels
Jan 4 at 7:20
If you update a signal in the sensitivity list, you will cause the process to be re-evaluated. It is possible to cause an infinite loop like this and cause a simulator to hit the iteration limit (and fail) or create a logic loop in real hardware.
– Tricky
Jan 4 at 9:17
If you update a signal in the sensitivity list, you will cause the process to be re-evaluated. It is possible to cause an infinite loop like this and cause a simulator to hit the iteration limit (and fail) or create a logic loop in real hardware.
– Tricky
Jan 4 at 9:17
Thank you, I understand now :)
– Florea Vlad
Jan 4 at 12:47
Thank you, I understand now :)
– Florea Vlad
Jan 4 at 12:47
add a comment |
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1
Yes. Your yes/no question snippet doesn't have the structure described in the title. See IEEE Std 1076-2008 10.2 Wait statement for the rules for constructing a sensitivity list. In -2008 you can use the reserved word
allto construct the sensitivity list from every signal evaluated in any process statement. Your snippet doesn't evaluate a. You'd get the process to resume needlessly once every time a is assigned and a is already '0'. An assignment schedules an update, if the value changes you get an event (14.7.3.4 Signal update) and the process resumes (14.7.5.3 Simulation cycle).– user1155120
Jan 4 at 0:46
You are probably looking for a variable in a process. Variables are updated immediately, but not at the next wait statement. Please not a process with sensitivity ist is equivalent to a process with a
wait on <signallist>;before theend process;– Paebbels
Jan 4 at 7:20
If you update a signal in the sensitivity list, you will cause the process to be re-evaluated. It is possible to cause an infinite loop like this and cause a simulator to hit the iteration limit (and fail) or create a logic loop in real hardware.
– Tricky
Jan 4 at 9:17
Thank you, I understand now :)
– Florea Vlad
Jan 4 at 12:47