What happens in CPU, cache and memory when CPU is instructed to store data to memory?
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Multi tool use
Let's suppose the memory hierarchy is 1 cpu with L1i, L1d ,L2i L2d,L3, DRAM.
I'm wondering what happens at the lower levels of the computer when I use MOV/store
instruction (or any other instruction that will cause CPU transfer data to memory)? I know what happens if there is just CPU and memory, but with the caches I'm a bit confused. I've searched for this, but it only yielded information about data transfer between:
- registers and memory
- CPU and cache,
- cache and memory
I'm trying to understand more about this, like when cache will write through, when will write back? I just know write through is that update cache line and corresponding memory line immediately and write back is that update until replacement.Can they coexist? Is it the data will transfer directly to memory in write through? and in write back the data will through cache hierarchy?
What caused my confusion is that the Volatile in C/C++.As I known those type of variable will store in memory directly which means don’t through cache.Am I right? So what if I define a Volatile variable and a normal variable like int . how can the CPU distinguish that write directly to memory or through cache hierarchy.
Is there any instruction that can control cache? If not, how is cache
controlled? Some other hardware? OS? Cache controller(if such a thing exists)?
caching memory architecture operating-system cpu
add a comment |
Let's suppose the memory hierarchy is 1 cpu with L1i, L1d ,L2i L2d,L3, DRAM.
I'm wondering what happens at the lower levels of the computer when I use MOV/store
instruction (or any other instruction that will cause CPU transfer data to memory)? I know what happens if there is just CPU and memory, but with the caches I'm a bit confused. I've searched for this, but it only yielded information about data transfer between:
- registers and memory
- CPU and cache,
- cache and memory
I'm trying to understand more about this, like when cache will write through, when will write back? I just know write through is that update cache line and corresponding memory line immediately and write back is that update until replacement.Can they coexist? Is it the data will transfer directly to memory in write through? and in write back the data will through cache hierarchy?
What caused my confusion is that the Volatile in C/C++.As I known those type of variable will store in memory directly which means don’t through cache.Am I right? So what if I define a Volatile variable and a normal variable like int . how can the CPU distinguish that write directly to memory or through cache hierarchy.
Is there any instruction that can control cache? If not, how is cache
controlled? Some other hardware? OS? Cache controller(if such a thing exists)?
caching memory architecture operating-system cpu
1
Yeah, the cache subsystem can be pretty complex in practice. Implementations details are often hard to find. A proper answer to your question will probably be too long so this site. Have you tried searching for a specific architecture? WB and WT can coexist in the sense that different mem regions can have different caching policy. I'd leavevolatile
completely out, it's hard to understand an a C++ concept anyway. You can try reading the Intel and AMD reference and optimisation manuals then search Google for specific terms.
– Margaret Bloom
Dec 30 '18 at 13:15
Thanks for your advice,and i tried to search some specific architecture,but i just get something that are not what i wanted. Could you tell me what key words should i search that can find a description about specific architecture .Appreciate
– tuffy chow
Jan 1 at 12:44
MIPS has many open implementations, you can Google along the lines "mips caches schematics" to get some results with an HW point of view. Removing "schematics" gives a more SW oriented POV. For x86 Googling "x86 cache lfb superqueue" for some implementation details. Eventually add "storebuffer". Information at the ISA level can be found in the manuals. In general googling "archname" + "cache hierarchy" (e.g. "arm cache hierarchy") is good starting point. Finally, patents are the last source of information if needed.
– Margaret Bloom
Jan 1 at 21:01
add a comment |
Let's suppose the memory hierarchy is 1 cpu with L1i, L1d ,L2i L2d,L3, DRAM.
I'm wondering what happens at the lower levels of the computer when I use MOV/store
instruction (or any other instruction that will cause CPU transfer data to memory)? I know what happens if there is just CPU and memory, but with the caches I'm a bit confused. I've searched for this, but it only yielded information about data transfer between:
- registers and memory
- CPU and cache,
- cache and memory
I'm trying to understand more about this, like when cache will write through, when will write back? I just know write through is that update cache line and corresponding memory line immediately and write back is that update until replacement.Can they coexist? Is it the data will transfer directly to memory in write through? and in write back the data will through cache hierarchy?
What caused my confusion is that the Volatile in C/C++.As I known those type of variable will store in memory directly which means don’t through cache.Am I right? So what if I define a Volatile variable and a normal variable like int . how can the CPU distinguish that write directly to memory or through cache hierarchy.
Is there any instruction that can control cache? If not, how is cache
controlled? Some other hardware? OS? Cache controller(if such a thing exists)?
caching memory architecture operating-system cpu
Let's suppose the memory hierarchy is 1 cpu with L1i, L1d ,L2i L2d,L3, DRAM.
I'm wondering what happens at the lower levels of the computer when I use MOV/store
instruction (or any other instruction that will cause CPU transfer data to memory)? I know what happens if there is just CPU and memory, but with the caches I'm a bit confused. I've searched for this, but it only yielded information about data transfer between:
- registers and memory
- CPU and cache,
- cache and memory
I'm trying to understand more about this, like when cache will write through, when will write back? I just know write through is that update cache line and corresponding memory line immediately and write back is that update until replacement.Can they coexist? Is it the data will transfer directly to memory in write through? and in write back the data will through cache hierarchy?
What caused my confusion is that the Volatile in C/C++.As I known those type of variable will store in memory directly which means don’t through cache.Am I right? So what if I define a Volatile variable and a normal variable like int . how can the CPU distinguish that write directly to memory or through cache hierarchy.
Is there any instruction that can control cache? If not, how is cache
controlled? Some other hardware? OS? Cache controller(if such a thing exists)?
caching memory architecture operating-system cpu
caching memory architecture operating-system cpu
edited Jan 2 at 14:35
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Mavi Domates
1,66511022
1,66511022
asked Dec 30 '18 at 12:35
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tuffy chowtuffy chow
11
11
1
Yeah, the cache subsystem can be pretty complex in practice. Implementations details are often hard to find. A proper answer to your question will probably be too long so this site. Have you tried searching for a specific architecture? WB and WT can coexist in the sense that different mem regions can have different caching policy. I'd leavevolatile
completely out, it's hard to understand an a C++ concept anyway. You can try reading the Intel and AMD reference and optimisation manuals then search Google for specific terms.
– Margaret Bloom
Dec 30 '18 at 13:15
Thanks for your advice,and i tried to search some specific architecture,but i just get something that are not what i wanted. Could you tell me what key words should i search that can find a description about specific architecture .Appreciate
– tuffy chow
Jan 1 at 12:44
MIPS has many open implementations, you can Google along the lines "mips caches schematics" to get some results with an HW point of view. Removing "schematics" gives a more SW oriented POV. For x86 Googling "x86 cache lfb superqueue" for some implementation details. Eventually add "storebuffer". Information at the ISA level can be found in the manuals. In general googling "archname" + "cache hierarchy" (e.g. "arm cache hierarchy") is good starting point. Finally, patents are the last source of information if needed.
– Margaret Bloom
Jan 1 at 21:01
add a comment |
1
Yeah, the cache subsystem can be pretty complex in practice. Implementations details are often hard to find. A proper answer to your question will probably be too long so this site. Have you tried searching for a specific architecture? WB and WT can coexist in the sense that different mem regions can have different caching policy. I'd leavevolatile
completely out, it's hard to understand an a C++ concept anyway. You can try reading the Intel and AMD reference and optimisation manuals then search Google for specific terms.
– Margaret Bloom
Dec 30 '18 at 13:15
Thanks for your advice,and i tried to search some specific architecture,but i just get something that are not what i wanted. Could you tell me what key words should i search that can find a description about specific architecture .Appreciate
– tuffy chow
Jan 1 at 12:44
MIPS has many open implementations, you can Google along the lines "mips caches schematics" to get some results with an HW point of view. Removing "schematics" gives a more SW oriented POV. For x86 Googling "x86 cache lfb superqueue" for some implementation details. Eventually add "storebuffer". Information at the ISA level can be found in the manuals. In general googling "archname" + "cache hierarchy" (e.g. "arm cache hierarchy") is good starting point. Finally, patents are the last source of information if needed.
– Margaret Bloom
Jan 1 at 21:01
1
1
Yeah, the cache subsystem can be pretty complex in practice. Implementations details are often hard to find. A proper answer to your question will probably be too long so this site. Have you tried searching for a specific architecture? WB and WT can coexist in the sense that different mem regions can have different caching policy. I'd leave
volatile
completely out, it's hard to understand an a C++ concept anyway. You can try reading the Intel and AMD reference and optimisation manuals then search Google for specific terms.– Margaret Bloom
Dec 30 '18 at 13:15
Yeah, the cache subsystem can be pretty complex in practice. Implementations details are often hard to find. A proper answer to your question will probably be too long so this site. Have you tried searching for a specific architecture? WB and WT can coexist in the sense that different mem regions can have different caching policy. I'd leave
volatile
completely out, it's hard to understand an a C++ concept anyway. You can try reading the Intel and AMD reference and optimisation manuals then search Google for specific terms.– Margaret Bloom
Dec 30 '18 at 13:15
Thanks for your advice,and i tried to search some specific architecture,but i just get something that are not what i wanted. Could you tell me what key words should i search that can find a description about specific architecture .Appreciate
– tuffy chow
Jan 1 at 12:44
Thanks for your advice,and i tried to search some specific architecture,but i just get something that are not what i wanted. Could you tell me what key words should i search that can find a description about specific architecture .Appreciate
– tuffy chow
Jan 1 at 12:44
MIPS has many open implementations, you can Google along the lines "mips caches schematics" to get some results with an HW point of view. Removing "schematics" gives a more SW oriented POV. For x86 Googling "x86 cache lfb superqueue" for some implementation details. Eventually add "storebuffer". Information at the ISA level can be found in the manuals. In general googling "archname" + "cache hierarchy" (e.g. "arm cache hierarchy") is good starting point. Finally, patents are the last source of information if needed.
– Margaret Bloom
Jan 1 at 21:01
MIPS has many open implementations, you can Google along the lines "mips caches schematics" to get some results with an HW point of view. Removing "schematics" gives a more SW oriented POV. For x86 Googling "x86 cache lfb superqueue" for some implementation details. Eventually add "storebuffer". Information at the ISA level can be found in the manuals. In general googling "archname" + "cache hierarchy" (e.g. "arm cache hierarchy") is good starting point. Finally, patents are the last source of information if needed.
– Margaret Bloom
Jan 1 at 21:01
add a comment |
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1
Yeah, the cache subsystem can be pretty complex in practice. Implementations details are often hard to find. A proper answer to your question will probably be too long so this site. Have you tried searching for a specific architecture? WB and WT can coexist in the sense that different mem regions can have different caching policy. I'd leave
volatile
completely out, it's hard to understand an a C++ concept anyway. You can try reading the Intel and AMD reference and optimisation manuals then search Google for specific terms.– Margaret Bloom
Dec 30 '18 at 13:15
Thanks for your advice,and i tried to search some specific architecture,but i just get something that are not what i wanted. Could you tell me what key words should i search that can find a description about specific architecture .Appreciate
– tuffy chow
Jan 1 at 12:44
MIPS has many open implementations, you can Google along the lines "mips caches schematics" to get some results with an HW point of view. Removing "schematics" gives a more SW oriented POV. For x86 Googling "x86 cache lfb superqueue" for some implementation details. Eventually add "storebuffer". Information at the ISA level can be found in the manuals. In general googling "archname" + "cache hierarchy" (e.g. "arm cache hierarchy") is good starting point. Finally, patents are the last source of information if needed.
– Margaret Bloom
Jan 1 at 21:01