Reading BROM value
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I am trying to read the value from the BROM which is generated using block memory generator IP in Vivado 2015.4. I initialize the value by using .coe file with given data. Below is my code for reading the value by increasing the address, but there is problem with the address which i cant get it right, because it has to be 0 for the first value as the initiation,does anyone knows how to deal with this problem, thank you very much.
`timescale 1 ns / 1 ps
module brom_tb();
reg clk;
reg en;
reg [15:0] addr;
wire [31:0] dout;
BROM_wrapper
uut(.BRAM_PORTA_addr(addr),.BRAM_PORTA_clk(clk),.BRAM_PORTA_dout(dout),
.BRAM_PORTA_en(en));
initial
begin
addr = 0;
clk = 1'b0;
en = 1'b1;
forever #4 clk=~clk;
end
always @(posedge clk)
begin
addr = addr + 1;
end
endmodule
This is my result
https://i.imgur.com/Xf13LPm.png
verilog fpga
asked Jan 4 at 17:18
Thịnh NguyễnThịnh Nguyễn
11
add a comment |
I am trying to read the value from the BROM which is generated using block memory generator IP in Vivado 2015.4. I initialize the value by using .coe file with given data. Below is my code for reading the value by increasing the address, but there is problem with the address which i cant get it right, because it has to be 0 for the first value as the initiation,does anyone knows how to deal with this problem, thank you very much.
`timescale 1 ns / 1 ps
module brom_tb();
reg clk;
reg en;
reg [15:0] addr;
wire [31:0] dout;
BROM_wrapper
uut(.BRAM_PORTA_addr(addr),.BRAM_PORTA_clk(clk),.BRAM_PORTA_dout(dout),
.BRAM_PORTA_en(en));
initial
begin
addr = 0;
clk = 1'b0;
en = 1'b1;
forever #4 clk=~clk;
end
always @(posedge clk)
begin
addr = addr + 1;
end
endmodule
This is my result
https://i.imgur.com/Xf13LPm.png
verilog fpga
asked Jan 4 at 17:18
Thịnh NguyễnThịnh Nguyễn
11
Your waveform shows the end (window range ~999.9975ns to 1ms), and your problem statement is about the initialization. We should be seeing the time window from 0 to 10ns. FYI sequential logic should be assigned with non-blocking assignment (<=)
– Greg
Jan 4 at 17:46
Thank you very much for your answer, there's something that I want to ask, when I run the simulation, how can I adjust the time so that when I run all, it will automatically increase the address and read out the value, which starts from 0 and go through all the address in BROM without restarting the clk. When i run all, the address seems to be random without increasing order. Thank you very much again. Here is the result when I run all i.imgur.com/k38WG5Q.png
– Thịnh Nguyễn
Jan 5 at 4:43
add a comment |
I am trying to read the value from the BROM which is generated using block memory generator IP in Vivado 2015.4. I initialize the value by using .coe file with given data. Below is my code for reading the value by increasing the address, but there is problem with the address which i cant get it right, because it has to be 0 for the first value as the initiation,does anyone knows how to deal with this problem, thank you very much.
`timescale 1 ns / 1 ps
module brom_tb();
reg clk;
reg en;
reg [15:0] addr;
wire [31:0] dout;
BROM_wrapper
uut(.BRAM_PORTA_addr(addr),.BRAM_PORTA_clk(clk),.BRAM_PORTA_dout(dout),
.BRAM_PORTA_en(en));
initial
begin
addr = 0;
clk = 1'b0;
en = 1'b1;
forever #4 clk=~clk;
end
always @(posedge clk)
begin
addr = addr + 1;
end
endmodule
This is my result
https://i.imgur.com/Xf13LPm.png
verilog fpga
asked Jan 4 at 17:18
Thịnh NguyễnThịnh Nguyễn
11
I am trying to read the value from the BROM which is generated using block memory generator IP in Vivado 2015.4. I initialize the value by using .coe file with given data. Below is my code for reading the value by increasing the address, but there is problem with the address which i cant get it right, because it has to be 0 for the first value as the initiation,does anyone knows how to deal with this problem, thank you very much.
`timescale 1 ns / 1 ps
module brom_tb();
reg clk;
reg en;
reg [15:0] addr;
wire [31:0] dout;
BROM_wrapper
uut(.BRAM_PORTA_addr(addr),.BRAM_PORTA_clk(clk),.BRAM_PORTA_dout(dout),
.BRAM_PORTA_en(en));
initial
begin
addr = 0;
clk = 1'b0;
en = 1'b1;
forever #4 clk=~clk;
end
always @(posedge clk)
begin
addr = addr + 1;
end
endmodule
This is my result
https://i.imgur.com/Xf13LPm.png
verilog fpga
verilog fpga
asked Jan 4 at 17:18
Thịnh NguyễnThịnh Nguyễn
11
asked Jan 4 at 17:18
Thịnh NguyễnThịnh Nguyễn
11
asked Jan 4 at 17:18
Thịnh NguyễnThịnh Nguyễn
11
asked Jan 4 at 17:18
Thịnh NguyễnThịnh Nguyễn
11
asked Jan 4 at 17:18
Thịnh NguyễnThịnh Nguyễn
11
11
Your waveform shows the end (window range ~999.9975ns to 1ms), and your problem statement is about the initialization. We should be seeing the time window from 0 to 10ns. FYI sequential logic should be assigned with non-blocking assignment (<=)
– Greg
Jan 4 at 17:46
Thank you very much for your answer, there's something that I want to ask, when I run the simulation, how can I adjust the time so that when I run all, it will automatically increase the address and read out the value, which starts from 0 and go through all the address in BROM without restarting the clk. When i run all, the address seems to be random without increasing order. Thank you very much again. Here is the result when I run all i.imgur.com/k38WG5Q.png
– Thịnh Nguyễn
Jan 5 at 4:43
add a comment |
Your waveform shows the end (window range ~999.9975ns to 1ms), and your problem statement is about the initialization. We should be seeing the time window from 0 to 10ns. FYI sequential logic should be assigned with non-blocking assignment (<=)
– Greg
Jan 4 at 17:46
Thank you very much for your answer, there's something that I want to ask, when I run the simulation, how can I adjust the time so that when I run all, it will automatically increase the address and read out the value, which starts from 0 and go through all the address in BROM without restarting the clk. When i run all, the address seems to be random without increasing order. Thank you very much again. Here is the result when I run all i.imgur.com/k38WG5Q.png
– Thịnh Nguyễn
Jan 5 at 4:43
Your waveform shows the end (window range ~999.9975ns to 1ms), and your problem statement is about the initialization. We should be seeing the time window from 0 to 10ns. FYI sequential logic should be assigned with non-blocking assignment (
<=)– Greg
Jan 4 at 17:46
Your waveform shows the end (window range ~999.9975ns to 1ms), and your problem statement is about the initialization. We should be seeing the time window from 0 to 10ns. FYI sequential logic should be assigned with non-blocking assignment (
<=)– Greg
Jan 4 at 17:46
Thank you very much for your answer, there's something that I want to ask, when I run the simulation, how can I adjust the time so that when I run all, it will automatically increase the address and read out the value, which starts from 0 and go through all the address in BROM without restarting the clk. When i run all, the address seems to be random without increasing order. Thank you very much again. Here is the result when I run all i.imgur.com/k38WG5Q.png
– Thịnh Nguyễn
Jan 5 at 4:43
Thank you very much for your answer, there's something that I want to ask, when I run the simulation, how can I adjust the time so that when I run all, it will automatically increase the address and read out the value, which starts from 0 and go through all the address in BROM without restarting the clk. When i run all, the address seems to be random without increasing order. Thank you very much again. Here is the result when I run all i.imgur.com/k38WG5Q.png
– Thịnh Nguyễn
Jan 5 at 4:43
add a comment |
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Your waveform shows the end (window range ~999.9975ns to 1ms), and your problem statement is about the initialization. We should be seeing the time window from 0 to 10ns. FYI sequential logic should be assigned with non-blocking assignment (
<=)– Greg
Jan 4 at 17:46
Thank you very much for your answer, there's something that I want to ask, when I run the simulation, how can I adjust the time so that when I run all, it will automatically increase the address and read out the value, which starts from 0 and go through all the address in BROM without restarting the clk. When i run all, the address seems to be random without increasing order. Thank you very much again. Here is the result when I run all i.imgur.com/k38WG5Q.png
– Thịnh Nguyễn
Jan 5 at 4:43